The present invention relates to a bus lock control apparatus required for semaphore management in a multiprocessor system having a common bus.
A conventional bus lock control apparatus has the following arrangement. A bus use request from each agent is sent to a bus arbiter, and the bus arbiter arbitrates the bus use requests of all agents. As a result of arbitration, the arbiter selects one of the agents which have sent the bus use requests, and sends a bus transmission enable signal to the selected agent. The selected agent reserves the right of bus use as a master agent until bus transmission is completed. During this transmission, the bus arbiter does not send a bus transmission enable signal to any other agent. Upon completion of the bus transmission by the master agent, the master agent loses the right of bus use. The bus arbiter performs bus arbitration again to determine a new master agent. In this manner, the bus arbiter and each agent repeat the above operation, so that a system having a common bus can be properly operated.
An operation performed when the master agent sends a bus lock request to the bus arbiter will be described below. When the bus arbiter sends a transmission enable signal in response to a bus lock request, the arbiter immediately interlocks the bus. In this interlocked state, bus arbitration is interrupted, and a bus transmission enable signal is sent back to only the master agent. The master agent does not lose the right of bus use upon completion of transmission of the bus lock request and keeps occupying the bus.
After the master agent outputs a bus lock release request and this bus cycle is completed, the bus arbiter releases the bus interlocked state and restarts bus arbitration. That is, use of the bus by only the master agent is allowed during the bus interlocked period.
In the conventional bus lock apparatus, the bus lock request is used as a lock read signal, and the bus lock release request is used as an unlock write signal. During an interval from the lock read signal to the unlock write signal, the bus is interlocked. When the master agent checks a memory content read out by the lock read signal and determines if the memory content is write-accessible, predetermined data is written again in a memory. However, if the memory content is not write-accessible, read data is written in the memory by the unlock write signal. This data is used to manage the semaphore in the memory. In the multiprocessor system, in order to prevent a plurality of processors from using the same semaphore, a use/nonuse state of the semaphore is represented by a semaphore header. Contention of the plurality of processors for this semaphore header is controlled such that the bus is interlocked using the lock read and unlock write signals to assure a sequence from a memory read operation to a memory write operation of each independent processor, thereby performing exclusive control.
A common bus system having a higher speed and a larger capacity than those of a conventional common bus system is proposed. In these bus arbitration systems, a plurality of bus cycles which overlap each other are generated in response to a bus cycle from the first initial resource use request transmission to response status reception in each bus arbitration system described above, thereby increasing the bus transfer speed. When a lock control system using a bus interlock scheme in such a bus arbitration system, the bus cycles cannot overlap each other, thus resulting in a contradiction.
When semaphore management is taken into consideration, the lock read and unlock write signals must always be used to access the semaphore header by OS address management, and normal read/write access is not performed. However, since the bus is interlocked, even a read/write bus cycle free from a semaphore influence cannot be sent out, and a bus throughput is decreased.